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is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 1 4mx18 , 2mx36 72mb ddr - iip (burst 2) cio synchronous sram (2. 0 cycle read latenc y) features ? 2mx36 and 4mx18 configuration available. ? on - chip delay - locked l oop (dll) for wide data valid window. ? common i/o read and write ports. ? synchronous pipeline read with self - timed late write operation. ? double data r ate (ddr) interface for read and write input ports. ? 2. 0 cycle read latency. ? fixed 2 - bit burst for read and write operations. ? clock stop support. ? two input clocks (k and k#) for a ddress and control registering at rising edges only. ? two echo clocks (cq and cq#) that are delivered simultaneously with data. ? +1.8v core power supply and 1.5, 1.8v vddq, used with 0.75, 0.9v vref. ? hstl input and output interface . ? registered addresses, wri te and read controls, byte writes, data in, and data outputs. ? full data coherency. ? boundary scan using limited set of jtag 1149.1 functions. ? byte write capability. ? fine ball grid array (fbga) package: 1 3 mmx1 5 mm and 15mmx17mm body size 165 - ball (11 x 15) ar ray ? programmable impedance output drivers via 5x user - supplied precision resistor. ? data valid pin (qvld). ? odt (on die termination) feature is supported optionally on data input, k/k#, and bw x # . ? the end of top mark (a/a1/a2) is to define options. is61ddp2b22m36a : dont care odt function and pin connection is61ddp2b22m36a1 : option1 is61ddp2b22m36a2 : option2 refer to more detail description at page 6 for each odt option. description the 72mb is61ddp2b2 2m36a /a1/a2 and is61ddp2b2 4m18a /a1/a2 are synchronous, high - performance cmos static random access memory (sram) devices. these srams have a common i/o bus. the rising edge of k clock initiates the read/write operation, and all internal operations are self - timed. refer to the timing reference diagram for truth table for a description of the basic operations of these ddr - ii p (burst of 2 ) cio srams. read and write addresses are registered on alternating rising edges of the k clock. reads and writes are performed in double data rate. the following are registered internally on the rising edge of the k clock: ? read/write address ? read enable ? write enable ? byte writ es ? data - in for first burst address ? da ta - out for first burst address the following are registered on the rising edge of the k # clock: ? byte writes ? da ta - in for second burst address ? data - out for second burst address byte writes can change with the corresponding data - in to enable or disable writes on a per - byte basis. an internal write buffer enables the data - ins to be registered one cycle after the write address. the first data - in burst is clocked one cycle later than the write command signal, and t he second burst is timed to the following rising edge of the k# clock. during the burst read operation, the data - outs from the first bursts are updated from output registers of the third rising edge of the k clock (starting two clock cycles later after re ad command). the data - outs from the second burst are updated with the third rising edge of the k # clock where read command receives at the first rising edge of k. the device is operated with a single +1.8v power supply and is compatible with hstl i/o inte rfaces. novem ber 2014 copyright ? 2013 integrated silicon solution, inc. a ll rights reserved. issi reserves the right to make changes to this specification and its products at any time without no tice. issi assumes no liability arising out of the application or use of any information, products or services described herein. custom ers are advised to obtain the latest version of this device spec ification before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. pr oducts are not authorized for use in such applications unless i ntegrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately pr otected under the circumstances
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 2 package ballout and description x36 fbga ball configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 a cq# nc/sa 1 sa r/w# bw 2 # k# bw 1 # ld# sa sa cq b nc dq27 dq18 sa bw 3 # k bw 0 # sa nc nc dq8 c nc nc dq28 v ss sa nc sa v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss vss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss vss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h d off # v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa qvld sa sa nc dq9 dq0 r tdo tck sa sa sa odt sa sa sa tms tdi n ote s: 1. the following balls are reserved for higher densities: 2a for 144 mb. x18 fbga ball configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 a cq# sa sa r/w# bw 1 # k# nc/sa 1 ld# sa sa cq b nc dq9 nc sa nc/sa 1 k bw 0 # sa nc nc dq8 c nc nc nc v ss sa nc sa v ss nc dq7 nc d nc nc dq10 v ss v ss v ss vss v ss nc nc nc e nc nc dq11 v ddq v ss v ss vss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h d off # v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa qvld sa sa nc nc dq0 r tdo tck sa sa sa odt sa sa sa tms tdi note s: 1. the following balls are r eserved for higher densities: 7a for 144m b , and 5b for 288m b .
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 3 ball descriptions symbol type description k, k# input input clock: this input clock pair registers address and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of k # . k # is ideally 180 degrees out of phase with k. all synchronous inputs must me et setup and hold times around the clock rising edges. these balls cannot remain vref level. cq, cq# output synchronous echo clock outputs: the edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals run freely and do not stop when q tri - states. doff# input dll disable and reset input : when low , this input causes the dll to be bypassed and reset the previous dll information. when high, dll will start operating and lock the frequency after tck lock time. the device behaves in one clock read latency mode when the dll is turned off. in this mode, the device can be operated at a frequency of up to 167 mhz . qvld output valid output indicator: the q valid indicates valid output data. qvld is edge aligned with cq and cq # . sa input synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of k . these inputs are ignored when device is deselected. d q 0 - d q n b idir data input and output signals. input data must meet setup and hold times ar ound the rising edges of k and k # during write operations. these pins drive out the requested d a ta when the read operation is active. valid o utput data is synchronized to the respec tive c q and c q . see ball configuration figures for ball site location of individual signals. the x 18 device uses d q 0~d q 17. d q 18~d q 35 should be treated as nc pin. the x 36 device uses d q 0~d q 35. r/ w# input synchronous read or write input. when ld# is low, this input designates the access type (read when it is high, write when it is low) for loaded address. r/w# must meet the setup and hold times around edge of k. ld # input synchronous load. this input is brought low when a bus cycle sequence is defined. this definition includes address and read/write direction . bw x # input synchronous byte writes: when low, these inputs cause their respective byte to be registered and written during wri te cycles. these signals are sampled on the same edge as the corresponding data and must meet setup and hold times ar ound the rising edges of k and # k for each of the two rising edges comprising the write cycle. see write truth table for signal to data rel ationship. v ref input reference hstl input reference voltage: nominally vddq/2, but may be adjusted to improve system noise margin. provides a reference voltage for the hstl input buffers. v dd power power supply: 1.8 v nominal. see dc characteristics and operating conditions for range. v ddq power power supply: isolated output buffer supply. nominally 1.5 v. see dc characteristics and operating conditions for range. v ss ground ground of the device zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. q and cq output impedance are set to 0.2 x rq, where rq is a resistor from this ball to ground. this ball can be connected directly to vddq, which enables the minimum impedance mode. this ball cannot be connected directly to vss or left unconnected. in odt (on die termination) enable devices, the odt termination values tracks the value of rq. the odt range is selected by odt control input. tms, tdi, tck input ieee1149.1 input pins for jtag . tdo out put ieee1149.1 output pin for jtag . nc n/a no connect: these signals should be left floating or connected to ground to improve package heat dissipation. odt input odt control; refer to sram features for the details.
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 4 sram features description block diagram note: numerical values in parentheses refer to the x18 device configuration . read operations the sram operates continuously in a burst - of - two mode. read cycles are started by registering r/w # in active high state at the rising edge of the k clock. k and k # , are also used to control the timing to the outputs. the data corresponding to the first address is clocked two cycles later by the rising edge of the k clock. the data c orresponding to the second burst is clocked two and half cycles later by the following rising edge of the k # clock. a set of free - running echo clocks, cq and cq # , are produced internally with timings identical to the data - outs. the echo clocks can be used as data capture clocks by the receiver device. whenever ld # is low, a new address is registered at the rising edge of the k clock. a nop operation (ld # is high) does not terminate the previous read. the output drivers disable automatically to a high - z sta te. write operations write operations can also be initiated at every other rising edge of the k clock whenever r/w# is low. the write address is also registered at that time. when the address needs to change, ld# needs to be low simultaneously to be regist ered by the rising edge of k. again, the write always occurs in bursts of two . because of its common i/o architecture, the data bus must be tri - stated at least one cycle before the new data - in is presented at the dq bus. the write data is provided in a late write mode; that is, the data - in corresponding to the first address o f the burst, is presented one clock cycle later or at the rising edge of the following k clock. the data - in corresponding to the second write burst address follows next, registered by the rising edge of k#. d a t a r e g i s t e r b u r s t 2 c o n t r o l l o g i c 2 0 ( 2 1 ) a d d r e s s e s 4 ( 2 ) l d # r / w # b w x # c l o c k g e n e r a t o r k k # 2 m x 3 6 ( 4 m x 1 8 ) m e m o r y a r r a y w r i t e d r i v e r a d d r e s s d e c o d e r s e n s e a m p l i f i e r s s e l e c t o u t p u t c o n t r o l 2 0 ( 2 1 ) 3 6 x 2 ( 1 8 x 2 ) 3 6 x 2 ( 1 8 x 2 ) 3 6 x 2 ( 1 8 x 2 ) o u t p u t s e l e c t 3 6 ( 1 8 ) d q ( d a t a - o u t & d a t a - i n ) c q , c q # ( e c h o c l o c k s ) i n p u t / o u t p u t d r i v e r / d o f f a d d r e g & b u r s t c o n t r o l 7 2 ( 3 6 ) o u t p u t r e g 3 6 ( 1 8 ) 3 6 ( 1 8 )
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 5 the data - in provided for writing is initially kept in write buffers. the information on these buffers is written into the array on the third write cycle. a read cycle to the last two write address produces data from the write buffers. similarly, a read address followed by the same write address produces the latest write data. the sram maintains data coherency. during a write, the byte writes independently control which byte of any of the two burst addresses is written . ( s ee x1 8/x36 write truth tables and timing reference diagram for truth table ) whenever a write is disabled (r/w# is high at the rising edge of k), data is not written into the memory. rq programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. for example, an rq of 250 results in a driver impedance of 50. the allowable range of rq to guarantee impedance matching is between 175 and 350 at v ddq =1.5v. the rq resistor should be placed less than two inches away from the zq ball on the sram module. the capacitance of the loaded zq trace must be less than 7.5 pf. the zq pin can also be directly connected to v ddq to obtain a minimum impedance setting. zq should not be connected to v ss . p rogrammable impedance and power - up requirements periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in su pply voltage and temperature. during power - up, the driver impedance is in the middle of allowable impedances values. the final impedance value is achieved within 1024 clock cycles. valid data indicator (qvld) a data valid pin (qvld) is available to assist in high - speed data output capture. this output signal is edge - aligned with the echo clock and is asserted high half a cycle before valid read data is available and asserted low half a cycle before the final valid read data arrives. d elay lock ed loop (dll) delay lock ed loop (dll) is a new system to align the output data coincident with clock rising or falling edge to enhance the output valid timing characteristics . it is locked to the clock frequency and is constantly adjusted to match the clock frequency . t herefore device can have stable output over the temperature and voltage variation . dll has a limitation of locking range and jitter adjustment which are specified as tkhkh and tkcvar respectively in the ac timing characteristics. in order to turn this feature off, applying logic low to the doff# pin will bypass this. in the dl l off m ode, the device behaves with one clock cycle latency and a longer access time which is known in ddr - i o r legacy quad mode. the dll can also be reset without power down by toggling doff# pin low to high or stopping the input clocks k and k# for a minimum of 30ns.(k and k# must be stayed either at higher than vih or lower than vil level. remaining vref is no t permitted.) dll reset must be issued when power up or when clock frequency changes abruptly . after dll being reset, it gets locked after 2048 cycles of stable clock.
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 6 odt (on die termination) on die termination (odt) is a feature that allows a sram to turn on/off termination resistance for odt pins. the odt feature is designed to improve signal integrity of the memory channel by allowing the sram controller to turn on/off termination resistance independently for any or all sram devices. odt can have thr ee status, high, low, and floating. each status can have different odt termination values which tracks the value of rq (see the picture below) in ddr - iip devices having common i/o bus, odt is automatically enabled at the write operation of sram and di sabled at the read operation of sram. fig 1 . functional representation of odt notes 1. allowable range of rq to guarantee impedance matching a tolerance of 20% is 175 ? is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 7 odt pins 1) odt pin in option1 . odt values of k, k#, d qs , and wx# are controlled by odt pin . . odt for dqs will be on and off depending on the status. read command will turn odt off as the following rule. off: first read command + read latency - 0.5 cycle on: last read command + read latency + bl/2 cycle + 0.5 cycle (see below timing chart) example1) bl=2, rl(read latency=2.5) example2) bl=4, rl(read latency=2.5) example3) bl=2, rl(read latency=2.0) 2) odt pin in option2 - . same odt pin rule of option1 applies except k and k#. k k# command dq(ddriip) dq odt rd a qa qa rd b rd c rd d qb qb qc qc qd qd wt e wt f wt g wt h rd i q q q rd j de de df df dg dg dh dh read latency=2.5 read latency=2.5 enable disable enable disable rl bl/2 0.5 rl - 0.5 k k# command dq(ddriip) dq odt q rd a qa qa rd c qa qa qc qc qc qc wt e wt g rd i q q de de de de dg dg dg dg read latency=2.5 read latency=2.5 enable disable enable rl bl/2 0.5 rl - 0.5 disable k k# command dq(ddriip) dq odt rd a qa qa rd b rd c rd d qb qb qc qc qd qd wt e wt f wt g wt h rd i q q q rd j de de df df dg dg dh dh read latency=2.0 read latency=2.0 enable disable enable disable rl bl/2 0.5 rl - 0.5
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 8 power - up and power - down sequences the recommendation of voltage apply sequence is : v dd v ddq 1) v ref 2) v in notes: v ddq can be applied concurrently with v dd . v ref can be applied concurrently with v ddq . after power and clock signals are stabilized, device can be ready for normal operation after tkc - lock cycles. in tkc - lock cycle period, device initializes internal logics and locks dll. depending on /doff status, locking dll will be skipped. the following timing pictures are possible examples of powe r up sequence. sequence1. /doff is fixed low after tkc - lock cycle of stable clock, device is ready for normal operation. note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of cases. sequence2. /doff is controlled and goes high after clock being stable. note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of cases. >tkc - lock for device initialization >tkc - lock for device initialization power on stage unstable clock period stable clock period read to use k k# vdd vddq vref vin power on stage unstable clock period stable clock period read to use k k# doff# vdd vddq vref vin
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 9 sequence3. /doff is controlled but goes high before clock being stable. because dll has a risk to be locked with the unstable c lock, dll needs to be reset and locked with the stable input. a) k - stop to reset. if k or k# stays at vih or vil for more than 30ns, dll will be reset and ready to re - lock. in tkc - lock period, dll will be locked with a new stable value. device can be rea dy for normal operation after that. note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of cases. a) /doff low to reset. if /doff toggled low to high, dll will be reset and ready to re - lock. in tkc - lock period, dll will be locked with a new stable value. device can be ready for normal operation after that. note) applying dll reset sequences (sequence 3a, 3b) are also required when operating frequency is changed without power off. note) all inputs including clocks must be either logically high or low during power on stage. timing above show s only one of cases. > 30ns >tkc - lock for device initialization > tdofflowtoreset >tkc - lock for device initialization power on stage unstable clock period k-stop stable clock period read to use k k# doff# vdd vddq vref vin power on stage unstable clock period doff reset dll stable clock period read to use k k# doff# vdd vddq vref vin
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 10 application example the following figure depicts an implementation of four 2m x 18 ddr - ii p srams with common i/os. s r a m # 1 s a r / w # l d # b w x # k / k # d q c q / c q # z q r q = 2 5 0 s r a m # 4 z q r q = 2 5 0 d a t a - i n & d a t a o u t a d d r e s s s r a m # 1 c q i n p u t s r a m # 4 c q i n p u t r e a d & w r i t e c o n t r o l n e w a d d r e s s c o n t r o l b y t e w r i t e c o n t r o l s o u r c e c l k m e m o r y c o n t r o l l e r v t v t r r = 5 0 r v t = v r e f s a r / w # l d # b w x # k / k # d q c q / c q # v t r
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 11 state diagram notes: 1. internal burst counter is fixed as two - bit linear; that is, when first address is a0+0, next internal burst address is a0+1. 2. read refers to read active status with r/w # = h igh. 3. write refers to write active status with r/ w # = low . 4. load refers to read new address act ive status with ld # = low. 5. load is read new address inactive status with ld = high. p o w e r - u p n o p l o a d n e w r e a d a d d r e s s d d r - i i r e a d d d r - i i w r i t e l o a d l o a d l o a d r e a d w r i t e / l o a d / l o a d / l o a d
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 12 timing reference diagram for truth table the timing reference diagram for truth table is helpful in understanding the clock and write truth tables , as it shows the cycle r elationship between clocks, address, data in, data out, and control signals . read command is issued at the beginning of cycle t. write command is issued at the beginning of cycle t+1. clock truth table (use the following table with the timing reference diagram for truth table .) mode clock controls data out / data in k ld# r/ w # q a / d b q a+1 / d b+1 stop clock stop x x previous state previous state no operation (nop) l h h x high - z high - z read a l h l h d out at k # (t+ 2 . 0 ) d out at k (t+ 2 . 5 ) write b l h l l d b at k (t+ 5 .0) d b at k # (t+ 5 .5) notes: 1. x = dont care; h = logic 1; l = logic 0. 2. a read operation is started when control signal r /w# is active high. 3. a write operation is started when control signal r/ w # is active low. 4. before entering into stop clock, all pending read and write commands must be completed. 5. for timing definitions, refer to the ac timing characteristics t able . signals must meet ac specifi cations at timings indicated in parenthesis with resp ect to switching clocks k and k# d b d b + 1 q a q a + 1 t + 1 t t + 2 t + 3 t + 4 t + 5 a b c y c l e k c l o c k k # c l o c k l d # r / w # b w x # a d d r e s s d a t a - i n / o u t ( d q ) c q c q # t c h q v 2 . 0 c y c l e s t + 2 . 5
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 13 x18 write truth table (use the following table with the timing reference diagram for truth table .) operation k (t+1.0) k (t+1.5) bw 0 bw 1 d b d b+1 write byte 0 l h l h d0 - 8 (t+4 .0) write byte 1 l h h l d9 - 17 (t+4 .0) write all bytes l h l l d0 - 17 (t+4 .0) abort write l h h h don't care write byte 0 l h l h d0 - 8 (t+4 .5) write byte 1 l h h l d9 - 17 (t+4 .5) write all bytes l h l l d0 - 17 (t+4 .5) abort write l h h h don't care notes: 1. for all cases, r/ w # needs to be active low during the rising edge of k occurring at time t. 2. for timing definitions refer to the ac timing characteristics table. signals must meet ac specifications with respect to switching clocks k and k # . x36 write truth table (use the following table with the timing reference diagram for truth table .) operation k (t+1.0) k (t+1.5) bw 0 bw 1 bw 2 bw 3 d b d b+1 write byte 0 l h l h h h d0 - 8 (t+4 .0) write byte 1 l h h l h h d9 - 17 (t+4 .0) write byte 2 l h h h l h d18 - 26 (t+4 .0) write byte 3 l h h h h l d27 - 35 (t+4 .0) write all bytes l h l l l l d0 - 35 (t+4 .0) abort write l h h h h h don't care write byte 0 l h l h h h d0 - 8 (t+4 .5) write byte 1 l h h l h h d9 - 17 (t+4 .5) write byte 2 l h h h l h d18 - 26 (t+4 .5) write byte 3 l h h h h l d27 - 35 (t+4 .5) write all bytes l h l l l l d0 - 35 (t+4 .5) abort write l h h h h h don't care notes: 1. for all cases, r/ w # needs to be active low during the rising edge of k occurring at time t. 2. for timing definitions refer to the ac timing characteristics table. signals must meet ac specifications with respect to switching clocks k and k # .
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 14 electrical specifications absolute maximum ratings parameter symbol min max units power supply voltage v dd ? 0. 5 2.9 v i/o power supply voltage v ddq ? 0.5 2.9 v dc input voltage v in ? 0.5 v dd + 0.3 v data out voltage v dout ? 0.5 2.6 v junction temperature t j - 110 c storage temperature t stg ? 55 + 125 c note: stresses greater than those listed in this table can cause permanent damage to the device. this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating temperature range temperature range symbol min max units commercial t a 0 +70 c industrial t a ? 40 +85 c dc electrical characteristics (over the operating temperature range, v dd =1.8v 5% ) parameter symbol min max units notes x36 average power supply operating current (i out =0, v in =v ih or v il ) i dd22 i dd25 i dd30 i dd33 ? 800 750 700 650 ma 1 ,2 x18 average power supply operating current (i out =0, v in =v ih or v il ) i dd22 i dd25 i dd30 i dd33 ? 750 700 650 60 0 ma 1 ,2 power supply standby current (r=v ih , w=v ih . all other inputs=v ih or v i l , i ih =0) i sb22 i sb25 i sb30 i sb33 ? 44 0 42 0 41 0 40 0 ma 1 ,2 input leakage current ( 0 v in v d dq for all input balls except v ref , zq , tck, tms, tdi ball) i li ? 2 +2 a 3, 4 output leakage current ( 0 v out v d dq for all output balls except tdo ball; output must be disabled. ) i lo ? 2 +2 a output high level voltage (i oh = ? 100ua, nominal zq) v oh v ddq ? 0. 2 v ddq v output low level voltage (i o l = 100ua, nominal zq) v ol v ss v ss +0. 2 v notes: 1. i out = chip output current. 2. the numeric suffix indicates the part operating at speed, as indicated in ac timing characteristics table (that is, i dd25 indicates 2.5ns cycle time). 3. odt must be disabled . 4. balls with odt and doff# do not follow this spec, i li = 100ua .
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 15 recommended dc operating conditions ( over the operating temperature range) parameter symbol min typical max units notes supply voltage v dd 1.8 C 5% 1. 8 1.8+5% v 1 output driver supply voltage v ddq 1.4 1.5 v dd v 1 input high voltage v ih v ref +0.1 - v ddq +0.2 v 1, 2 input low voltage v il C 0.2 - v ref C 0.1 v 1, 3 input reference voltage v ref 0.68 0.75 0.95 v 1, 5 clock signal voltage v in - clk C 0.2 - v ddq +0.2 v 1, 4 notes: 1. all voltages are referenced to v ss . all v dd , v ddq , and v ss pins must be connected. 2. v ih (m ax) ac = see 0vershoot and undershoot timings . 3. v il (m in) ac = see 0vershoot and undershoot timings . 4. v in - clk specifies the maximum allowable dc excursions of each clock (k and k# ). 5. peak - to - peak ac component superimposed on vref may not exceed 5% of vref . overshoot and undershoot timings 2 0 % m i n c y c l e t i m e v d d q v d d q + 0 . 6 v v i h ( m a x ) a c o v e r s h o o t t i m i n g 2 0 % m i n c y c l e t i m e g n d g n d - 0 . 6 v v i l ( m i n ) a c u n d e r s h o o t t i m i n g
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 16 typical ac input characteristics parameter symbol min max units notes ac input logic high v ih ( ac ) v ref + 0.2 v 1 , 2, 3, 4 ac input logic low v il ( ac ) v ref C 0.2 v 1, 2, 3, 4 clock input logic high v ih - clk ( ac ) v ref + 0.2 v 1, 2, 3 clock input logic low v il - clk ( ac ) v ref C 0.2 v 1, 2, 3 notes: 1. the peak - to - peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. performance is a function of v ih and v il levels to clock inputs. 3. see the ac input definition diagram. 4. see the ac input definition diagram. the signals should swing monotonically with no steps rail - to - rail with input signals never ringing back past v ih (ac) and v il (ac) during the input setup and input hold window. v ih ( ac) and v il (ac) are used for timing purposes only. ac input definition pbga thermal characteristics parameter symbol 13x15 bga 15x17 bga units thermal resistance ( junction to ambient at airflow = 1m/s) r ja 16.7 16.0 c/w thermal resistance ( junction to pins ) r jb 2.25 1.80 c/w thermal resistance ( junction to case ) r jc 3.11 2.87 c/w note: these parameter s are guaranteed by design and tested by a sample basis only. k # v r e f k v r a i l v i h ( a c ) v r e f v i l ( a c ) v - r a i l s e t u p t i m e h o l d t i m e
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 17 pin capacitance parameter symbol test condition max units input or output capacitance except dq pins c in , c o 5 pf d q capacitance (d q 0 C d q x ) c dq 6 pf clocks capacitance (k, k, c, c) c clk 4 pf note: these parameter s are guaranteed by design and tested by a sample basis only. programmable impedance output driver dc electrical characteristics (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v ) parameter symbol min max units notes output logic high voltage v oh v ddq /2 - 0.12 v ddq /2 + 0.12 v 1, 3 output logic low voltage v ol v ddq /2 - 0.12 v ddq /2 + 0.12 v 2, 3 notes: 1. 2. 3. parameter tested with rq=250 and v ddq =1.5v ac test conditions (over the operating temperature range, v dd =1.8v 5%, v ddq = 1.5v/1.8v ) parameter symbol conditions units notes output drive power supply voltage v ddq 1.5/1.8 v input logic high voltage v ih v ref + 0 .5 v input logic low voltage v il v ref C 0.5 v input reference voltage v ref 0.75/0.9 v input rise time t r 2.0 v/ ns input fall time t f 2.0 v/ ns output timing reference level v ref v clock reference level v ref v output load conditions 1, 2 note s : 1. see ac test loading. 2. parameter tested with rq= 250 and v ddq = 1 .5v ? ? ? ? ? ? ? ? ? ? ? ? ? 5 rq 2 v | i | ddq oh ? ? ? ? ? ? ? ? ? ? ? ? ? 5 rq 2 v | i | ddq ol
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 18 ac test loading (a) unless otherwise noted, ac test loading assume this condition. (b) tchqz and tchqx1 are specified with 5pf load capacitance and measured when transition occurs 100mv from the steady state voltage. (c)tdo 5 0 v r e f t e s t c o m p a r a t o r o u t p u t 5 0 v r e f v r e f 1 0 0 m v t e s t c o m p a r a t o r 5 0 5 p f v r e f o u t p u t v r e f t e s t c o m p a r a t o r o u t p u t 5 0 2 0 p f 5 0 v r e f
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 19 ac timing characteristics (over the operating temperature range, v dd =1.8v 5%, v ddq = 1.5v/1.8v ) parameter symbol 22 (450mhz) 25 (400mhz) 30 ( 333 mhz) 33 (300mhz) units notes min max min max min max min max clock clock cycle time (k, k#) tkhkh 2.2 8.40 2.50 8.40 3.00 8.4 3.33 8.4 ns clock phase jitter (k, k#) tkc var 0. 15 0. 15 0. 15 0. 20 ns 4 clock high time (k, k#) tkhkl 0.4 0.4 0.4 0.4 cycle clock low time (k, k#) tklkh 0.4 0.4 0.4 0.4 cycle clock to clock# (k, k#) tkhk#h 0.99 1.10 1.35 1.50 ns dll lock time (k) tkc lock 2048 2048 2048 2048 cycles 5 doff low period to dll reset tdofflowtoreset 5 5 5 5 ns k static to dll reset tkcreset 30 30 30 30 ns output times k, k# high to output valid tchqv 0.45 0.45 0.45 0.45 ns k, k# high to output hold tchqx - 0. 45 - 0. 45 - 0. 45 - 0.45 ns k, k# high to echo clock valid tchcqv 0.45 0.45 0.45 0.45 ns k, k# high to echo clock hold tchcqx - 0. 45 - 0. 45 - 0. 45 - 0.45 ns cq, cq# high to output valid tcqhqv 0. 2 0. 2 0.25 0.27 ns 6 cq, cq# high to output hold tcqhqx - 0. 2 - 0. 2 - 0.25 - 0.27 ns 6 k, high to output high - z tchqz 0.45 0.45 0.45 0.45 ns k, high to output low - z tchqx1 - 0. 45 - 0. 45 - 0. 45 - 0.45 ns cq, cq# high to qvld valid tqvld - 0.20 0.20 - 0.20 0.20 - 0.25 0.25 - 0.27 0.27 ns setup times address valid to k rising edge tavkh 0. 30 0. 40 0.4 0 0.4 0 ns r#,w# c ontrol input s valid to k rising edge tivkh 0. 30 0. 40 0.4 0 0.4 0 ns 2 bw x # c ontrol inputs valid to k rising edge tivkh 2 0.2 5 0.2 8 0.3 0 0.3 0 ns 2 data - in valid to k, k# rising edge tdvkh 0.2 5 0.2 8 0.3 0 0.3 0 ns hold times k rising edge to address hold tkhax 0. 30 0. 40 0.4 0 0.4 0 ns 2 k rising edge to r#,w# control inputs hold tkhix 0. 30 0. 40 0.4 0 0.4 0 ns 2 k rising edge to bw x # control inputs hold tkhix 2 0.2 5 0.2 8 0.3 0 0.3 0 ns k, k# rising edge to data - in hold tkhdx 0.2 5 0.2 8 0.3 0 0.3 0 ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. during normal operation, vih, vil, trise, and tfall of inputs must be within 20% of vih, vil, trise, and tfall of clock. 3. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. v dd slew rate must be less than 0.1v dc per 50ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 5. the data sheet parameters reflect tester guard bands and test setup variations . 6. to avoid bus contention, at a given voltage and temperature tchqx1 is bigger than tchqz. the specs as shown do not imply bus contention because tch qx1 is a min parameter that is worst case at totally different test conditions (0 c, 1.9v) than tchqz, which is a max paramet er (worst case at 70 c, 1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature .
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 20 read, write, and nop timing diagram notes: 1. q1 - 0 refers to the output from address a 1 . q 1 - 1 refers to the output from the next burst address following a 1 . 2 . the nop cycle is not necessary for correct device operation, however, at high clock frequencies, it might be required to prevent bus contention. a 1 k k # l d # a d d r e s s ( s a + s a 0 ) d q s c q c q # 1 2 3 4 5 6 7 r e a d n o p w r i t e t k h k h 2 . 0 c y c l e r e a d l a t e n c y 8 9 t k h k l t k l k h t k h k # h t i v k h t k h i x t c h q v t c h q x t c h q x 1 t c h q z u n d e f i n e d d o n t c a r e r / w # a 3 r e a d 1 0 1 1 n o p ( n o t e 2 ) a 5 t c h q v t c h c q v t c h c q x t c q h q v t c q h q x t d v k h t k h d x 1 2 a 2 t a v k h t k h a x a 4 w r i t e r e a d n o p q 1 - 0 q 1 - 1 q 2 - 0 q 2 - 1 t c h q x t c h c q v t c h c q x d 3 - 0 d 3 - 1 d 4 - 0 d 4 - 1 t c h q v q 5 - 0 q 5 - 1 t c h q x t c h q x 1 t c h q v t q v l d t q v l d q v l d t q v l d t q v l d
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 21 ieee 1149.1 serial boundary scan of jtag these srams incorporate a serial boundary scan test access port (tap) controller in 165 fbga package. that is fully compliant with ieee standard 1149.1 - 2001. the tap controller operates using standard 1.8 v interface logic levels. disabling the jtag feature these srams operate without using the jtag feature. to disable the tap controller, tck mus t be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. test access port signal list: test clock (tck) the test clock is to operate only tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is to set commands of the tap controller and is sampled on the rising edge of tck. this pin can be left unconnected at sram operation. the pin is pulled up internally to keep logic high level. t est data - in (tdi) the tdi pin is to receive serially input information into the instruction and data registers. it can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register (refer to the tap controller state diagram ) . tdi is internally pulled up and can be unconnected at sram. tdi is connected to the most significant bit (msb) on any register. test data - out (tdo) the tdo pin is to drive serially clock data out from the jtag registers. the output is active, depending upon the current state of the tap state machine (refer to instruction codes). the output changes on the falling edge of tck. tdo is con nected to the least significant bit (lsb) of any register.
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 22 tap controller state and block diagram tap controller state machine b y p a s s r e g i s t e r ( 1 b i t ) i d e n t i f i c a t i o n r e g i s t e r ( 3 2 b i t s ) i n s t r u c t i o n r e g i s t e r ( 3 b i t s ) t a p c o n t r o l l e r t d o t m s t c k t d i c o n t r o l s i g n a l s b o u n d a r y s c a n r e g i s t e r ( 1 0 9 b i t s ) . . . t e s t l o g i c r e s e t s e l e c t d r r u n t e s t i d l e 0 1 1 c a p t u r e d r 0 1 0 0 1 0 1 1 0 s h i f t d r e x i t 1 d r p a u s e d r e x i t 2 d r 1 1 u p d a t e d r 0 s e l e c t i r 1 c a p t u r e i r 0 1 0 0 1 0 1 s h i f t i r e x i t 1 i r p a u s e i r e x i t 2 i r 1 1 u p d a t e i r 0 0 0 1 0 1 0
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 23 performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and can be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. ins truction register this register is loaded during the update - ir state of the tap controller. three - bit instructions can be serially loaded into the instruction register. at power - up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture - ir state, the two lsbs are loaded with a binary 01 pattern to allow for fault isolation of th e board - level serial test data path. bypass register the bypass register is a single - bit register that can be placed between the tdi and tdo balls. it is to skip certain chips without serial boundary scan. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output balls on the sram. several no connected(nc) balls are also include d in the scan register to reserve other product options. the boundary scan register is loaded with the contents of the sram input and output ring when the tap controller is in the capture - dr state and is then placed between the tdi and tdo balls when the c ontroller is moved to the shift - dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the input and output ring. each bit corresponds to one of the balls on the sram package. the msb of the register is conne cted to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor - specific, 32 - bit code during the capture - dr state when the idcode command is loaded in the instruction register. the idcode is hardwired int o the sram and can be shifted out when the tap controller is in the shift - dr state. the id register has a vendor id code and other information tap instruction set tap instruction set is available to set eight instructions with the three bit instruction reg ister and all combinations are listed in the tap instruction code table. three of listed instructions on this table are reserved and must not be used. instructions are loaded serially into the tap controller during the shift - ir state when the instruction r egister is placed between tdi and tdo. to execute an instruction once it is shifted in, the tap controller must be moved into the update - ir state. idcode the idcode instruction causes a vendor - specific, 32 - bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift - dr state. the idcode instruction is loaded into the instruction register upon pow er - up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift - dr state. the sample z command puts the output bus into a high z state until the next command is supplied during the update ir state .
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 24 sample/preload sample/preload is a ieee 1149.1 basic instruction which connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift - dr state.. a snapshot of data on the inputs and output balls is captured in the boundary scan register when the tap controller is in a shift - dr state . the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture - dr state, an input or output will undergo a transition. the tap may then try to capture a signal w hile in transition. this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to ensure that the boundary scan register will capture the correct value of a signal, the sram signa l must be stabilized long enough to meet the tap controllers capture setup plus hold time. the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/ preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift - dr state. this places the boundary scan register between the tdi and tdo balls. preload places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. the shifting of data f or the sample and preload phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift - dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. private do not use these instructions. they a re reserved for future use and engineering mode. extest the extest instruction drives the preloaded data out through the system output pins. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift - dr controller state. ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tri - state mode. the boundary scan register has a special bit located at bit #109. when this scan cell, called the extest output bus tri - s tate, is latched into the preload register during the update - dr state in the tap controller, it directly controls the state of the output (q - bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to driv e the output bus. when low, this bit places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell during the shift - dr state. during update - dr, the valu e loaded into that shift - register cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q - bus pins. note that this bit is pre - set low to enable the output when the device is powered up, and al so when the tap controller is in the test - logic - reset state. jtag dc operating characteristics (over the operating temperature range , v dd =1.8v5% ) parameter symbol min max units notes jtag input high voltage v ih1 1.3 v dd +0.3 v jtag input low voltage v il1 C 0.3 0.5 v jtag output high voltage v oh1 1.4 - v |i oh1 | = 2ma jtag output low voltage v ol1 - 0.4 v i ol1 = 2m a jtag output high voltage v oh2 1.6 - v |i oh 2 | =100u a jtag output low voltage v ol2 - 0.2 v i ol 2 =100ua jtag input leakage current i lijtag - 100 +100 u a 0 vin vdd jtag output leakage current i lojtag - 5 +5 u a 0 vout vdd notes: 1. all voltages referenced to vss (gnd) ; all jtag inputs and outputs are lvttl - compatible .
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 25 jtag ac test conditions (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v ) parameter symbol conditions units input pulse high level v ih1 1.3 v input pulse low level v il1 0.5 v input rise time t r1 1.0 ns input fall time t f1 1.0 ns input and output timing reference level 0.9 v jtag ac characteristics (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v ) parameter symbol min max units tck cycle time t thth 50 C ns tck high pulse width t thtl 20 C ns tck low pulse width t tlth 20 C ns tms setup t mvth 5 C ns tms hold t thmx 5 C ns tdi setup t dvth 5 C ns tdi hold t thdx 5 C ns capture setup t cvth 5 C ns capture hold t thcx 5 C ns tck low to valid data* t tlov C 10 ns tck low to invalid data* t tlqx 0 C ns note: see ac test loading (c) jtag timing diagram t c k t m s t t h t h t t h t l t t l t h t t h m x t m v t h t d i t d o t t l o v t t h d x t d v t h t t l o x
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 26 instruction set code instruction tdo output 000 extest boundary scan register 001 idcode 32 - bit identification register 010 sample - z boundary scan register 011 private do not use 100 sample (/preload) boundary scan register 101 private do not use 110 private do not use 111 bypass bypass register id register definition revision number (31:29) part configuration (28:12) vendor id code (11:1) start bit (0) 000 0tdef0wx0 1p q l bts0 00011010101 1 part configuration definition: 1. def = 001 for 18mb, 010 for 36mb, 011 for 72mb 2. wx = 11 for x36, 10 for x18 3. p = 1 for ii+(quad - p/ddr - iip) , 0 for ii(quad/ddr - ii) 4. q = 1 for quad, 0 for ddr - ii 5. l = 1 for rl=2.5, 0 for rl2.5 6. b = 1 for burst of 4, 0 for burst of 2 7. s = 1 for separate i/o, 0 for common i/o 8. t = 1 for odt option, 0 for no odt option
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 27 boundary scan exit order order pin id order pin id order pin id 1 6r 37 10d 73 2c 2 6p 38 9e 74 3e 3 6n 39 10c 75 2d 4 7p 40 11d 76 2e 5 7n 41 9c 77 1e 6 7r 42 9d 78 2f 7 8r 43 11b 79 3f 8 8p 44 11c 80 1g 9 9r 45 9b 81 1f 10 11p 46 10b 82 3g 11 10p 47 11a 83 2g 12 10n 48 10a 84 1h 13 9p 49 9a 85 1j 14 10m 50 8b 86 2j 15 11n 51 7c 87 3k 16 9m 52 6c 88 3j 17 9n 53 8a 89 2k 18 11l 54 7a 90 1k 19 11m 55 7b 91 2l 20 9l 56 6b 92 3l 21 10l 57 6a 93 1m 22 11k 58 5b 94 1l 23 10k 59 5a 95 3n 24 9j 60 4a 96 3m 25 9k 61 5c 97 1n 26 10j 62 4b 98 2m 27 11j 63 3a 99 3p 28 11h 64 2a 100 2n 29 10g 65 1a 101 2p 30 9g 66 2b 102 1p 31 11f 67 3b 103 3r 32 11g 68 1c 104 4r 33 9f 69 1b 105 4p 34 10f 70 3d 106 5p 35 11e 71 3c 107 5n 36 10e 72 1d 108 5r 109 internal notes: 1. nc pins as defined on the fbga ball assignments are read as dont cares. 2. sta te of internal pin (#109) is loa ded via jtag
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 28 ordering information commercial range: 0c to +70 c speed order part no. organization package 450 mhz is61ddp2b22m36a/a1/a2 - 450m3 2mx36 165 fbga (15x17 mm) is61ddp2b22m36a/a1/a2 - 450m3l 2mx36 165 fbga (15x17 mm), lead free is61ddp2b24m18a/a1/a2 - 450m3 4mx18 165 fbga (15x17 mm) is61ddp2b24m18a/a1/a2 - 450m3l 4mx18 165 fbga (15x17 mm), lead free 400 mhz is61ddp2b22m36a/a1/a2 - 400m3 2mx36 165 fbga (15x17 mm) is61ddp 2 b22m36a/a1/a2 - 400m3l 2mx36 165 fbga (15x17 mm), lead free is61ddp 2 b24m18a/a1/a2 - 400m3 4mx18 165 fbga (15x17 mm) is61ddp 2 b24m18a/a1/a2 - 400m3l 4mx18 165 fbga (15x17 mm), lead free 333 mhz is61ddp 2 b22m36a/a1/a2 - 333 m3 2mx36 165 fbga (15x17 mm) is61ddp 2 b22m36a/a1/a2 - 333 m3l 2mx36 165 fbga (15x17 mm), lead free is61ddp 2 b24m18a/a1/a2 - 333 m3 4mx18 165 fbga (15x17 mm) is61ddp 2 b24m18a/a1/a2 - 333 m3l 4mx18 165 fbga (15x17 mm), lead free 3 00 mhz is61ddp 2 b22m36a/a1/a2 - 3 00m3 2mx36 165 fbga (15x17 mm) is61ddp 2 b22m36a/a1/a2 - 3 00m3l 2mx36 165 fbga (15x17 mm), lead free is61ddp 2 b24m18a/a1/a2 - 3 00m3 4mx18 165 fbga (15x17 mm) is61ddp 2 b24m18a/a1/a2 - 3 00m3l 4mx18 165 fbga (15x17 mm), lead free commercial range: c to +70 c speed order part no. organization package 450 mhz is61ddp 2 b22m36a/a1/a2 - 450 b4 2mx36 165 fbga (13x15 mm) is61ddp 2 b22m36a/a1/a2 - 450 b4 l 2mx36 165 fbga (13x15 mm), lead free is61ddp 2 b24m18a/a1/a2 - 450 b4 4mx18 165 fbga (13x15 mm) is61ddp 2 b24m18a/a1/a2 - 450 b4 l 4mx18 165 fbga (13x15 mm), lead free 400 mhz is61ddp 2 b22m36a/a1/a2 - 400 b4 2mx36 165 fbga (13x15 mm) is61ddp 2 b22m36a/a1/a2 - 400 b4 l 2mx36 165 fbga (13x15 mm), lead free is61ddp 2 b24m18a/a1/a2 - 400 b4 4mx18 165 fbga (13x15 mm) is61ddp 2 b24m18a/a1/a2 - 400 b4 l 4mx18 165 fbga (13x15 mm), lead free 333 mhz is61ddp 2 b22m36a/a1/a2 - 333b4 2mx36 165 fbga (13x15 mm) is61ddp 2 b22m36a/a1/a2 - 333b4 l 2mx36 165 fbga (13x15 mm), lead free is61ddp 2 b24m18a/a1/a2 - 333b4 4mx18 165 fbga (13x15 mm) is61ddpb24m18a/a1/a2 - 333b4 l 4mx18 165 fbga (13x15 mm), lead free 3 00 mhz is61ddp 2 b22m36a/a1/a2 - 3 00 b4 2mx36 165 fbga (13x15 mm) is61ddp 2 b22m36a/a1/a2 - 3 00 b4 l 2mx36 165 fbga (13x15 mm), lead free is61ddp 2 b24m18a/a1/a2 - 3 00 b4 4mx18 165 fbga (13x15 mm) is61ddp 2 b24m18a/a1/a2 - 3 00 b4 l 4mx18 165 fbga (13x15 mm), lead free
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 29 industrial range: - 40c to +85c speed order part no. organization package 450 mhz is61ddp 2 b22m36a/a1/a2 - 450m3i 2mx36 165 fbga (15x17 mm) is61ddp 2 b22m36a/a1/a2 - 450m3li 2mx36 165 fbga (15x17 mm), lead free is61ddp 2 b24m18a/a1/a2 - 450m3i 4mx18 165 fbga (15x17 mm) is61ddp 2 b24m18a/a1/a2 - 450m3li 4mx18 165 fbga (15x17 mm), lead free 400 mhz is61ddp 2 b22m36a/a1/a2 - 400m3i 2mx36 165 fbga (15x17 mm) is61ddp 2 b22m36a/a1/a2 - 400m3li 2mx36 165 fbga (15x17 mm), lead free is61ddp 2 b24m18a/a1/a2 - 400m3i 4mx18 165 fbga (15x17 mm) is61ddp 2 b24m18a/a1/a2 - 400m3li 4mx18 165 fbga (15x17 mm), lead free 333 mhz is61ddp 2 b22m36a/a1/a2 - 333 m3i 2mx36 165 fbga (15x17 mm) is61ddp 2 b22m36a/a1/a2 - 333 m3li 2mx36 165 fbga (15x17 mm), lead free is61ddp 2 b24m18a/a1/a2 - 333 m3i 4mx18 165 fbga (15x17 mm) is61ddp 2 b24m18a/a1/a2 - 333 m3li 4mx18 165 fbga (15x17 mm), lead free 3 00 mhz is61ddp 2 b22m36a/a1/a2 - 3 00m3i 2mx36 165 fbga (15x17 mm) is61ddp 2 b22m36a/a1/a2 - 3 00m3li 2mx36 165 fbga (15x17 mm), lead free is61ddp 2 b24m18a/a1/a2 - 3 00m3i 4mx18 165 fbga (15x17 mm) is61ddp 2 b24m18a/a1/a2 - 3 00m3li 4mx18 165 fbga (15x17 mm), lead free industrial range: - 40c to +85c speed order part no. organization package 450 mhz is61ddp 2 b22m36a/a1/a2 - 450 b4i 2mx36 165 fbga (13x15 mm) is61ddp 2 b22m36a/a1/a2 - 450 b4 l i 2mx36 165 fbga (13x15 mm), lead free is61ddp 2 b24m18a/a1/a2 - 450 b4i 4mx18 165 fbga (13x15 mm) is61ddp 2 b24m18a/a1/a2 - 450 b4 l i 4mx18 165 fbga (13x15 mm), lead free 400 mhz is61ddp 2 b22m36a/a1/a2 - 400 b4i 2mx36 165 fbga (13x15 mm) is61ddp 2 b22m36a/a1/a2 - 400 b4 l i 2mx36 165 fbga (13x15 mm), lead free is61ddp 2 b24m18a/a1/a2 - 400 b4i 4mx18 165 fbga (13x15 mm) is61ddp 2 b24m18a/a1/a2 - 400 b4 l i 4mx18 165 fbga (13x15 mm), lead free 333 mhz is61ddp 2 b22m36a/a1/a2 - 333b4i 2mx36 165 fbga (13x15 mm) is61ddp 2 b22m36a/a1/a2 - 333b4 l i 2mx36 165 fbga (13x15 mm), lead free is61ddp 2 b24m18a/a1/a2 - 333b4i 4mx18 165 fbga (13x15 mm) is61ddp 2 b24m18a/a1/a2 - 333b4 l i 4mx18 165 fbga (13x15 mm), lead free 3 00 mhz is61ddp 2 b22m36a/a1/a2 - 3 00 b4i 2mx36 165 fbga (13x15 mm) is61ddp 2 b22m36a/a1/a2 - 3 00 b4 l i 2mx36 165 fbga (13x15 mm), lead free is61ddp 2 b24m18a/a1/a2 - 3 00 b4i 4mx18 165 fbga (13x15 mm) is61ddp 2 b24m18a/a1/a2 - 3 00 b4 l i 4mx18 165 fbga (13x15 mm), lead free
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 30 package drawing C 1 5 x1 7 x1. 4 bga
is61ddp 2 b2 4 m18a/a1/a2 is61ddp 2 b2 2 m36a/a1/a2 integrated silicon solution, inc. - www.issi.com rev. a 09/20 /2014 31 package drawing C 13x15x1. 4 bga

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